Synchronized Access to Shared Memory by Multiple Essay

Synchronized Access to Shared stock by Multiple - Essay Example various techniques which finish be used to achieve this are discussed in the following paper.A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores (norm every(prenominal)y a CPU) into a single package composed of a single integrated circuit (IC). The below diagram Dual CPU Core Chip (Schmitz, 2004) gives an idea or so it.The principle behind current Multi-Processing (MP) systems is that computations requiring large amount of CPU usage could be broken up into many relatively independent parts. These parts, called threads, while universe executed simultaneously, could either be of the same or different process. Since these threads could be inter-dependant, issues of depot architecture and in particular retention consistency and lay aside behavior are key to both correctness and performance in multi-processing systems.Multi-Core Processors (CMPs) could be broadly classified as Uniform memory board Access (UMA) processors in which all the CPUs are able to access all the memory with no specific preference or Non-Uniform Memory Access (NUMA) processors, where each CPU may suck its own special memory area. A system may maintain memory consistency using hardware or using a combine of hardware and software techniques. Hardware can provide a particular memory ordinance guarantee, (hardware will maintain the sequential nature of program memory accesses), while software can be used supplement hardware-provided memory ordering by forcing additional ordering restrictions at desired times. The memory ordering scheme implemented is a design choice involving a tradeoff between hardware complexity, software complexity, and the desired ability to cache and buffer data.Non-Uniform Memory Access (NUMA) ArchitectureRefer Diagram NUMA Architecture. (Watson, n.d., p. 4) In NUMA architecture a processor can access its own local memory faster than non-local memory that is, memory local to an opposite processor or memory shared between processors. In this type, all the MPs may or may not be of similar capacity (Asymmetric Multi Processing). Communication between processors is often based on use of shared memory between those processors. An Inter Process Interrupt (IPI) allows CPUs to generate notifications to other CPUs to invalidate entries for a shared region or to request termination.Uniform Memory Access (UMA) ArchitectureRefer Diagram UMA Architecture. (Watson, n.d., p. 3) When multiple processors can access the same shared memory, the MP system has to make sure that the ordering of memory access from one processor is made visible to the other processors.Memory FencingOne way to achieve Cache Coherence in a MP environment would be by using Fencing technique. Refer Diagram MFDA and MFDR education (Mittal, 1997, p. 26). In this technique, MP system (11) access and release of shared memory space (15) is done using two special instructions - MFD A and MFDR. The Memory fence in Directional - Acquire (MFDA) (16) instruction locks the specified area from being accessed by other processors. Once the operation is over and data can be released, the Memory Fence Directional - Release (MFDR) (17) instruction is issued. Since an MFDA instruction locks the shared data until its